Frequency synthesis is a critical part of electronics circuits and, more particularly radio based electronics that operate over multiple frequencies. In that aspect Phase Locked Loops (PLL) have played quite a prominent role in the development of radio, wireless and telecommunications circuits.
FIG. 1 recalls the general principle of a classical PLL structure which can be used in frequency synthesis. A reference oscillator 1 provides a reference signal carrying a frequency fref which is divided by N1 by means of a divider 2 and then presented at a phase detector 3 which also receives the output of a second divider 6 performing a division by a factor N2. The output of phase detector 3 is presented at the input of a loop filter, e.g. a low pass filter, before entering into a Voltage Controlled Oscillator 5 generating the output signal fout which is also forwarded to the input of divider circuit 6. Such basic arrangement can be used for generating an output frequency fout=fref×(N2/N1).
Thanks to such PLL circuit, one may produce high frequency oscillations in a large number of electronics circuits and components and particularly radio transmitters and receivers.
Despite the efficiency of the PLL technique, there is still a difficulty in designing RF synthesizer simultaneously providing stability, low phase noise, accuracy and wide range of tuning, which may extend over more than an octave.
Indeed, the more accurate VCO and reference oscillators generally operate in a limited range of frequency and, furthermore, show to be quite expensive, thus increasing the manufacturing costs of the final product.
Consequently, there is still a need to provide an PLL circuit architecture which operates in a wide range of frequencies—over one octave—and which achieves at the same time stability, accuracy as well as low phase noise.